CYBERNETICS AND CONTROL THEORY

M. A. KARTSEV

THE PRINCIPLE OF MOVABLE INTERLOCKS IN THE CONSTRUCTION OF CIRCUITS OF ELECTRONIC DIGITAL COMPUTERS

(Presented by Academician S. L. Sobolev, 5 IV 1960)

The author of the present work, together with a group of engineers,* has developed a system of potential semiconductor circuit elements intended for use in electronic computing machines at switching frequencies of up to 5–7 MHz. Without dwelling on technical details, we shall note only certain characteristic features of this system of elements that are essential for the further exposition.

The basis of the system of elements consists of two circuits: a voltage-level inverter-shaper, which carries out the logical operation “not” and performs the functions of restoring signal levels, and a multistage diode logic circuit (in practice, a four-stage logic circuit “and—or—and—or,” having up to 4–6 inputs at each stage). The connections between the elements are made in such a way that the output signal of a diode logic circuit always goes to the input of an inverter-shaper, while the signal from the output of an inverter-shaper always goes to the inputs of diode logic circuits.

From elements of these two types, connected in the manner indicated, all circuits of the arithmetic devices and control devices of a computing machine can be constructed. For example, Fig. 1 shows the construction of a flip-flop—an element for storing one binary digit, having two stable states. Crossed feedbacks are closed through diode logic circuits. At the “free” inputs of “and” elements (i.e., at those inputs that are not occupied in the feedback circuit), a voltage corresponding to the signal “1” is normally maintained; at the “free” inputs of “or” elements, a voltage corresponding to the signal “0” is maintained. In order to set the flip-flop to a definite state (“0” or “1”), it is necessary either to apply the signal “1” to one of the free inputs of the “or” elements (the so-called “direct inputs of the flip-flop”), or to apply the signal “0” to one of the free inputs of the “and” elements (“inverse inputs of the flip-flop”).

A change in the combination of voltages at the inputs of a diode logic circuit appears at the output of the inverter-shaper connected with it always with some time delay—of the order of 20–30 nsec. In this case the main part of the delay is due to the inverter-shaper; the delay in the diode circuit is insignificant.

As is seen from Fig. 1, applying the signal “0” simultaneously to one of the inverse inputs for setting one and to one of the inverse inputs for setting zero breaks the crossed feedbacks in the flip-flop and frees both inverter-shapers. Each of them can then perform independent logical functions. For applying signals to them, the free inputs of the “or” elements may be used.

In the circuit of a computing machine, especially in the control circuits, there is a considerable number of flip-flops, each of which, in the operating cycle of the ma-

* V. L. Brailovskii, Yu. N. Glukhov, A. V. Datsko, E. F. Stupin, and G. I. Tanetov.

buses is used only during a short interval of time. The possibility of using the equipment included in the trigger circuit to perform various other functions may prove useful from the point of view of reducing the amount of equipment.

On the other hand, circuits can be constructed so that any pair of inverter-formers, for a certain combination of signals, is closed into a trigger or, perhaps, several inverter-formers are closed into a digital element with several stable states.

Circuits in which there are no digital elements fixed once and for all, but instead it is possible to establish feedbacks and thus introduce interlocks in various combinations of inverters, we shall call circuits with movable interlocks.

For an illustration of the possibilities provided by the use of the principle of movable interlocks, let us consider the circuit of Fig. 2. For simplicity, the diode circuits in this figure are shown as two-stage, and their “free” inputs (those not used in the interlock circuits) are omitted.

Fig. 1. Trigger. \(A\) — inverter-former, \(B\) — “or” element, \(V\) — “and” element

The control signals are denoted by \(x, y\), and \(z\). If all three control signals are absent (i.e., if \(x = y = z = 0\)), then the feedbacks are broken and each of the inverters can be used independently. If signal \(x\) is present, but \(y\) and \(z\) are absent \((x = 1,\ y = z = 0)\), then inverters 1 and 2 form a trigger, while inverter 3 is free. In the presence of signal \(y\) and in the absence of \(x\) and \(z\), the trigger is formed by inverters 1 and 3, and inverter 2 is free; in the presence of signal \(z\) and in the absence of \(x\) and \(y\), the trigger is formed by inverters 2 and 3, and inverter 1 is free. If two control signals are present simultaneously, then all three inverters are connected into an asymmetric trigger. For example, in the presence of control signals \(x\) and \(y\) \((x = y = 1,\ z = 0)\), inverter 1 forms one arm of the trigger, and inverters 2 and 3, connected as if in parallel, form the other arm. Finally, if all three control signals are present simultaneously \((x = y = z = 1)\), the circuit forms a three-position ring (an element with three stable states).

In those devices where, in order to ensure sufficient reliability, 100-percent equipment redundancy is necessary, it is usually necessary at least to double the number of triggers; this makes it possible to realize two combinations of equipment. By using, instead of an ordinary trigger, the circuit of Fig. 2, one can increase the amount of equipment not twofold but only one and a half times, and at the same time obtain the possibility of realizing the same two combinations of equipment*. With such use of the circuit, the voltage levels \(x\), \(y\), and \(z\) must be switched manually, from the control panel. Switching can be carried out on the fly, without stopping the automatic execution of operations, and in such a way that no failures occur at the moment of switching.

* This possibility was suggested to the author by A. B. Zalkind.

For example, if the flip-flops were formed by inverters 1 and 2, and inverters 3 were in reserve (i.e., if voltage \(x\) was switched on, and voltages \(y\) and \(z\) were switched off), and if it is desired to put inverters 3 into operation and place inverters 2 in reserve, then the switching must be carried out in the following order: 1) switch voltage \(y\) on to the diode circuits operating on inverters 3; 2) switch voltage \(y\) on to the diode circuits operating on inverters 1; 3) switch voltage \(x\) off from the diode circuits operating on inverters 1; 4) switch voltage \(x\) off from the diode circuits operating on inverters 2. As a result of the first stage of switching, inverters 3 begin to repeat the state of inverters 2; the second stage of switching closes the connections from the outputs of inverters 3 to the inputs of inverters 1, which for the time being operate in parallel with the connections from inverters 2; at the third stage the connections from inverters 2 to inverters 1 are broken, but inverters 2 still continue to repeat the state of inverters 3; finally, at the fourth stage inverters 2 are completely released.

Fig. 2. Circuit using the principle of movable interlocks (notations are the same as in Fig. 1)

As a second example, let us consider the construction of a shift register.

In ordinary potential-type circuits, an auxiliary register with the same number of flip-flops as in the main register is used to carry out the shift. The shift is then performed in two cycles. It is possible to reduce the number of auxiliary flip-flops by half, but in that case the shift will be performed not in two but in three cycles: 1) transfer of the states of the odd flip-flops of the main register into the auxiliary flip-flops; 2) transfer of the states of the even flip-flops of the main register into the odd flip-flops; 3) transfer of the states of the auxiliary flip-flops into the even flip-flops of the main register. If each flip-flop consists of two inverters, then in all, in the latter circuit, an average of three inverters per digit of the shift register is required. With the same number of inverters, but using the principle of movable interlocks, one can construct a more elegant circuit of a shift register—a register with moving flip-flops.

Let all the inverters be numbered in order: ..., 1, 2, 3, 4, 5, 6, ... . Through diode circuits the output signal of each \(i\)-th inverter can be transmitted to the inputs of two neighboring inverters—the \((i-1)\)-st and the \((i+1)\)-st. But these connections are closed only in the presence of certain signals. The control signals are distributed among the diode logic circuits with periodicity 3; this means that those signals which control the connections of the 1st inverter, in exactly the same way control the connections of the 4th, 7th, 10th, etc. inverters; those signals which control the connections of the 2nd inverter are applied in exactly the same way to the 5th, 8th, 11th, ... inverters, and so on.

In the initial position the combination of control signals is such that flip-flops are formed by pairs of inverters 1 and 2, 4 and 5, 7 and 8, and so on. These flip-flops store the initial number. In addition, the output signal of the 2nd inverter controls the 3rd inverter, so that the state of the 3rd inverter coincides with the state of the 1st inverter; the output signal of the 5th inverter controls the 6th inverter, so that the states of the 6th and 4th inverters coincide, and so on. The initial state may be represented conventionally by the scheme

\[ \ldots 1 \rightleftarrows 2 \to 3 \quad 4 \rightleftarrows 5 \to 6 \quad 7 \rightleftarrows 8 \to 9 \ldots, \tag{0} \]

where the numbers correspond to the ordinal numbers of the inverters, and the arrows indicate the connections between them.

The execution of the shift begins with the switching on of such a control signal that establishes a connection from the 3rd inverter to the 2nd, from the 6th to the 5th, etc. As a result, at the first stage the circuit takes the form

\[ \ldots\ 1 \rightleftarrows 2 \rightleftarrows 3 \quad 4 \rightleftarrows 5 \rightleftarrows 6 \quad 7 \rightleftarrows 8 \rightleftarrows 9 \ldots \tag{1} \]

Now in each digit we have asymmetric triggers; one arm of the triggers is formed by inverters \(2, 5, 8, \ldots\), while the other arm is formed by pairs of inverters connected as if in parallel \((1—3, 4—6, 7—9, \ldots)\).

Then the combination of control signals is changed so that the connections between the 1st and 2nd, 4th and 5th, 7th and 8th, ... inverters are broken, while a connection is established from the 3rd inverter to the 4th, from the 6th to the 7th, etc. Now the circuit takes the form

\[ \ldots \to 1 \quad 2 \rightleftarrows 3 \to 4 \quad 5 \rightleftarrows 6 \to 7 \quad 8 \rightleftarrows 9 \to \ldots \tag{2} \]

The position after the 2nd stage is analogous to the initial position, but all the triggers have been shifted by one inverter to the right. The subsequent stages of the change of the circuit in the process of carrying out the shift look as follows:

\[ \ldots \rightleftarrows 1 \quad 2 \rightleftarrows 3 \rightleftarrows 4 \quad 5 \rightleftarrows 6 \rightleftarrows 7 \quad 8 \rightleftarrows 9 \rightleftarrows \ldots \tag{3} \]

\[ \ldots \rightleftarrows 1 \to 2 \quad 3 \rightleftarrows 4 \to 5 \quad 6 \rightleftarrows 7 \to 8 \quad 9 \rightleftarrows \ldots \tag{4} \]

\[ \ldots \rightleftarrows 1 \rightleftarrows 2 \quad 3 \rightleftarrows 4 \rightleftarrows 5 \quad 6 \rightleftarrows 7 \rightleftarrows 8 \quad 9 \rightleftarrows \ldots \tag{5} \]

\[ \ldots 1 \rightleftarrows 2 \to 3 \quad 4 \rightleftarrows 5 \to 6 \quad 7 \rightleftarrows 8 \to 9 \ldots \tag{6} \]

At the last stage the circuit turns out to be exactly the same as in the initial position, but all the information has moved (together with the triggers) by one digit to the right. Although the shift is carried out here in 6 stages, and not in 3 as in the ordinary circuit with an analogous amount of equipment (in the circuit with half the number of auxiliary triggers), the circuit under consideration nevertheless gives a certain gain in speed, since each of the stages here may be much shorter than in the ordinary circuit.

Another feature of the shift-register circuit under consideration consists in the fact that a shift in the opposite direction can be carried out in it without any complications, simply by switching on the same control signals in the other sequence.

The examples given show that the use of the principle of movable interlocks makes it possible to construct qualitatively new circuits. The possibilities for applying this principle are, of course, far from being exhausted by the two cases considered. The most interesting applications will probably be connected with the construction of self-learning automata. In the initial period of operation, an automaton performs a large number of logical operations in search of the correct line of behavior. For this purpose, large and complex logical circuits must be provided in it. As experience accumulates, some of the elements of the logical circuits are placed under interlock and turn into memory elements: in the process of “learning,” the amount of information that must be remembered grows, while the complexity of the logical operations that must be performed in order to make one decision or another gradually decreases. When external conditions change, such connections may completely or partially disintegrate, with the capabilities of the logical circuits again increasing; then, as the automaton adapts to the new conditions, interlocks are once again established between individual elements. It is possible that in devices imitating the nervous system it will be useful, along with a large number of mutually duplicating logical circuits, to have the possibility of temporarily closing some of the elements of these circuits into triggers or rings for memorizing certain information, and then again switching them into logical circuits.

Institute of Electronic Control Machines
Academy of Sciences of the USSR

Received
25. III. 1960