CYBERNETICS AND CONTROL THEORY

G. M. Adelson-Velsky, A. L. Brudno, A. S. Kronrod,
P. T. Reznikovsky

ON AN INSTRUCTION SYSTEM FOR A THREE-ADDRESS MACHINE WITHOUT AN ADDRESS REGISTER

(Presented by Academician M. V. Keldysh on 27 VII 1963)

1°. The exposition is for a machine with 4096 memory cells containing 43-bit words. Machine-distinguished cells are: \(S\), the standard end \(\Omega\), and the unforgettable zero in the zero cell.

2°. Bits in words are numbered from right to left; \(A_k\) denotes the \(k\)-th bit of the word \(A\). Words may be interpreted:

a) as instructions \((A_{43} \div A_{37}\) — code, \(A_{36} \div A_{25}\) — address I, \(A_{24} \div A_{13}\) — address II, \(A_{12} \div A_1\) — address III).

b) as numbers in normal form \((A_{43}\) — sign, \(A_{42} \div A_{37}\) — order \(+ 100_8\), further — mantissa).

c) as positive integer 43-bit numbers.

3°. Everywhere the following notation is used: \(KA\) is the code of the word \(A\); \(\operatorname{Ad} A\) is the address part of \(A\) (from \(A_1\) to \(A_{36}\)). The I–III addresses of the word \(A\) are denoted \(A1, A2, A3\). In the case of possible ambiguity, the 12-bit number constituting \(As\) is denoted by “\(As\).” The address of the cell containing the word \(A\) is denoted by \(A0\). Everywhere \(\alpha, \beta, \gamma, \delta\), and \(\varepsilon\) denote, respectively, 1, 2, 3, 6, and 7 bits taken consecutively. The cell containing the instruction under consideration is denoted by \(Я\), and the one following it by \(Я + 1\).

4°. The instruction system is given in the table. In the text, explanations are given only for instructions that are not clear from the table. Work with external devices and block memory is not considered.

5°. Explanations to the code table

The immediate-execution instruction \(НИ\, A,B,C\) (001) executes the instruction from the cell \(A3 + \langle B\rangle\). Before this, “\(C\)” enters the address register of the instruction.

\(\operatorname{Prf}[A],\ B = C\) (002) serves to form the addresses of the cell \(C\) by algebraic addition of the addresses (and the code) \(B\). Let

\[ A = \alpha_0 \beta_0 \alpha_1 \beta_1 \alpha_2 \beta_2 \alpha_3 \beta_3. \]

Then “\(Bs\)” \(\times (-1)^{\alpha_s}\) is an addend for \(C\beta_s\) \((s = 1,2,3)\). If \(\beta_s = 0\), the number “\(Bs\)” is not used. \(KC = KB\) when \(\alpha_0 = \beta_0 = 0\), and \(KC = 0\) in all other cases. If \(\beta_0 \ne 0\), the quantity \(KB \times (-1)^{\alpha_0}\) is an addend for \(C\beta_0\).

The instruction \(\Phi(A,B,C)\) (003), executed immediately after \(\operatorname{Inf}\ ABC\) (103), makes it possible to refer in one instruction to a function of one variable with specification of the addresses of the argument and of the result.

The address-formation instruction (004). Let

\[ \begin{aligned} Я: &\quad \Phi A,\quad A,\quad B,\quad C,\\ Я + 1: &\quad K,\quad P,\quad Q,\quad R. \end{aligned} \]

The instruction \((K,\ P + \langle A3\rangle,\ Q + \langle B3\rangle,\ R + \langle C3\rangle)\) will be executed, with the address register of the instruction containing not \(Я\), but \(Я + 1\).

The instruction-formation instruction (005). Let

\[ \begin{aligned} Я: &\quad \Phi K\quad \alpha'_1 \alpha'_2 \alpha'_3 \alpha_1 \beta_1 \alpha_2 \beta_2 \alpha_3 \beta_3\quad M\quad T,\\ Я + 1: &\quad K\quad L_1\quad L_2\quad L_3. \end{aligned} \]

If \(T \ne 0\), the instruction

\[ KT = K,\qquad Ts = Ms \cdot \alpha_s' + (-1)^{\alpha_s}\cdot Ls\,\gamma_s \]

will enter the cell \(T\).

If \(T = 0\), then the instruction formed in the indicated way will not be written into memory, but will be executed immediately, as one located in \(Я + 1\).

Example.

\[ \begin{aligned} Я: &\quad \Phi K\ 101\ 13\ 02\ 00\ S\ T\\ Я + 1: &\quad \times\qquad A\qquad B\ C \end{aligned} \]

the command \((S1 - A3) \times B2 = (S3 + \text{“}C\text{”})\) will enter \(T\).

Group operation (006). Let

\[ \begin{array}{rcccc} Я: & ГOП & \alpha_0\beta_0\alpha_1\beta_1\alpha_2\beta_2\alpha_3\beta_3 & B & C\\ Я+1: & \ldots & \ldots & \ldots & \ldots \end{array} \]

Then the command located in \(Я+1\) is executed in a cycle “\(C\)” times if \(\beta_0=0\), and \(C\beta_0\) times if \(\beta_0 \ne 0\). To the \(s\)-th execution address of \(Я+1\), at each step there is added \((-1)^s\cdot\text{“}B\beta_s\text{”}\) if \(\alpha_0=1,\ \beta_s\ne 0\), and \((-1)^s\cdot\text{“}B\text{”}\) if \(\alpha_0=0,\ \beta_s\ne 0\). If \(\beta_s=0\), the \(s\)-th execution address of \(Я+1\) is not changed. At the end of the cycle, control passes to \(Я+2\), unless in the cycle it has been transferred to another command. The command \(Я+1\) itself remains unchanged.

Cut-out \([\delta_1\delta_2]\wedge B=C\) (044). If \(\delta_1\leqslant\delta_2\), then \(C_i=B_i\) for \(\delta_1\leqslant i\leqslant\delta_2\) and \(C_i=0\) for \(i<\delta_1\) or \(i>\delta_2\). If \(\delta_1>\delta_2\), then \(C_i=B_i\) for \(i\geqslant\delta_1\) or \(i\leqslant\delta_2\), and \(C_i=0\) for \(\delta_2<i<\delta_1\).

Complex shift \([A]\Rightarrow B=C\) (045). Let \(A=\alpha_{-1}\alpha_0\alpha_1\alpha_2\alpha_3\varepsilon\). Let \(\tau=\varepsilon-100_8\).

The shift is by \(|\tau|\) digits to the left for \(\tau\geqslant0\) and to the right for \(\tau<0\). Shifted are: the code \(B\) if \(\alpha_0\ne0\), and the addresses \(Bs\) for which \(\alpha_s\ne0\). Let \(M\) be the set of numbers of digits subject to shifting. Let \(T_i=1\) for \(i\in M\) and \(T_i=0\) for \(i\notin M\). Into \(C\) goes \(Q\), the shifted part of \(B\), intersected with \(T\). If \(\alpha_{-1}=1\), then the unshifted part of \(B\) is also added to \(Q\). Command 145 is executed analogously. Control is transferred to \(C\) when \(Q=0\).

Shifts by address (046, 146, 047, and 147). Let \(\tau=\text{“}A3\text{”}-100_8\). The shift is by \(|\tau|\) digits to the left for \(\tau\geqslant0\) and to the right for \(\tau<0\). The commands \(A_3\to B=C\) and \(A_3\to B; C\) (046 and 146) shift the whole word \(B\), while \(A_3\Rightarrow, B=C\) and \(A_3\Rightarrow, B; C\) (047 and 147) shift only the address part of \(B\), with \(KC=KB\).

Commands \(A\mathbin{\underline{\pm}}_i\text{“}B\text{”}\) (051—053; 151—153 and 061—063) are executed as follows: \(Ai\mathbin{\underline{\pm}}\text{“}B\text{”}=Ci\). The remaining addresses and the code of \(C\) coincide with the code and the corresponding addresses of \(A\).

Commands \(A\mathbin{\underline{\pm}}_{i3}B\) (054—056, 154—156 and 064—066) add (subtract) “\(B3\)” to \(Ai\); the remaining addresses and the code are preserved.

Assembly Сб \([A],\,B=C\) (170) and disassembly Рзб \([A],\,B=C\) (171). Let \(i_1<i_2<\cdots<i_k\) be the numbers of all digits of \(A\) for which \(A_{i_s}\ne0\). Then in assembly \(C_s=B_{i_s}\) for \(s\leqslant k\) and \(C_s=0\) for \(s>k\), while in disassembly \(C_{i_s}=B_s\) \((1\leqslant s\leqslant k)\), and the remaining digits of \(C\) are equal to 0. Selection of the most significant one. St. ed. \(A,B,C\) (174). Let \(\lambda=\max i\ (A_i=1)\). Then \(B_\lambda=1;\ B_s=0\ (s\ne\lambda),\ KC=C1=C2=0\) and \(C3=\lambda\).

Count \([\delta_1\delta_2]\wedge B=C\) (175). If \(\delta_1\leqslant\delta_2\), the number of digits \(B_i=1\) for \(\delta_1\leqslant i\leqslant\delta_2\) is placed in \(C3\), and if \(\delta_1\geqslant\delta_2\), the number of digits \(B_i=1\) for \(i\geqslant\delta_1\) and \(i\leqslant\delta_2\). In both cases \(KC=C1=C2=0\).

6°. In addition to the designated cells \(0\), \(S\), and \(\Omega\), it is useful to have also a “stopwatch” \(T\)—a counter cell in which the right 10—12 digits are electronic. To this counter, upon execution of each command (or, still better, of a standard cycle), 1 is added.

7°. It is important that numbers of cells be assigned to the command register, to several RAM units, and to the register containing in address III the address of the preceding command.

8°. When operations with normalized numbers are performed, an emergency stop must occur upon an attempt to operate on the number \(-0\) (zero in the result of a floating-point operation must be issued as \(+0\)). This same number, as a command, is a stop. Provision should be made for memory layout—0 from the console.

Institute of Theoretical and Experimental Physics
of the State Committee for the Utilization of Atomic Energy
Institute of Electronic Control Machines
Central Scientific-Research Institute of Complex Automation

Received
8 VII 1963